In the manufacturing process of semiconductor devices, various kinds of tests are performed in each process and the test results are fed back in order to remove a defective product and to improve yields. For example, an operation test to inspect whether the semiconductor device operates normally and whether the specifications are met is performed and only those having passed the test are shipped.
As the circuit scale of a LSI increases, it becomes difficult to detect the internal operation state, and therefore, a scan circuit is formed within the semiconductor device in order to detect the internal operation state. The scan circuit is a shift register in which flip-flop circuits (FF) are continuously connected in the form of a chain and each FF sends data from the previous stage or data of a combinational circuit (logic circuit) captured at a certain point of time to the next stage in synchronization with a clock. FF in the initial stage sends data input to the input terminal to the next stage in place of the data from the previous stage. FF in the final stage outputs the output data to the output terminal. By utilizing the scan circuit, it is possible to set desired data in the combinational circuit and to output a state (data) of the combinational circuit at a certain point of time to the outside. Due to this, it is possible to know the operational state of the combinational circuit at a desired point of time by operating the combinational circuit from a desired state.
The scan circuit is normally formed by FFs used when performing the normal operation (system operation) within the semiconductor device, however, there is a case where FFs provided in order to form the scan circuit are used. In a large-scale LSI, the number of FFs forming the scan circuit is tremendous and the time taken to shift data from the initial stage to the final stage becomes long, and therefore, there is a case, for example, where a plurality of scan chains are formed. However, if the number of scan chains increases, the number of input and output terminals for the scan chains also increases accordingly and the number of pads also increases, and therefore, the number of scan chains is set appropriately.
In recent years, in the miniaturized LSI whose scale has been increased, the failure of the scan circuit brings about a problem. If a failure occurs in the scan circuit, the logic scan test is no longer significant, and as a result of this, it is difficult to estimate the fault location of LSI. With the test circuit by the normal scan chain, it is difficult to analyze the scan chain failure after the development of LSI, and therefore, the necessity for the scan circuit having a function to make clear the cause of the scan chain failure (resulting from manufacture and resulting from design) is increased.